1. Field of the Invention
This invention relates to the construction of a device known as WSI (wafer scale integration) comprising an integrated circuit formed on a wafer and having a unified function.
2. Description of the Background Art
There is a semiconductor device comprising an integrated circuit formed on a single wafer and having a single unified function, such as a CPU (central processing unit) or a microprocessor, which is realized by developing the concept of LSI (large scale integration). Such a semiconductor device is called WSI (wafer scale integration).
An example of known WSI devices is shown in FIGS. 13 and 14. FIG. 13 is a diagrammatic plan of a wafer 1 of the WSI device. FIG. 14 is a schematic perspective view of a WSI package 2 for fitting the wafer 1. The WSI wafer 1 is constructed to be dish-shaped. On the main surface of the WSI wafer 1 is formed an integrated circuit including a multiplicity of logic circuits and the like. A plurality of wire bonding pads 3 are arranged peripherally of the wafer 1.
The WSI package 2 includes a die pad 5 centrally of a package body 4 for supporting the WSI wafer 1. The package body 4 mainly comprises a multi-layer ceramic board. A plurality of inner leads 6 are formed peripherally of the die pad 5. When the WSI wafer 1 is mounted on the die pad 5, the inner leads 6 are opposed to the wire bonding pads 3 of the WSI wafer 1. The inner leads 6 and wire bonding pads 3 are wired together. Further, a seal ring 7 is formed peripherally of, the inner leads 6. The seal ring 7 maintains gas tightness between a lid (not shown) and the package body 4 as assembled. A plurality of outer pins 8 are formed underneath the package body 4. These outer pins 8 are electrically connected through the inner leads 6 to the wire bonding pads 3 of the WSI wafer 1.
FIGS. 15 and 16 show another example of known WSI devices. This WSI device is in the form of a wafer having a substantially square main surface. Its basic construction is the same as that of the foregoing example.
The above WSI devices have the following constructional features as compared with LSI devices:
(1) Because of the numerous logic circuits and memory circuits, a multiplicity of pads are required for communicating signals with the exterior.
(2) It is difficult to shorten the wiring extending to the pads in order to reduce access time on the wafer.
(3) Since individual WSI devices are expensive, a high manufacturing yield is required.
(4) Since many functions are involved, circuit tests are carried out through a plurality of processes for individual functional units.
The WSI device comprises an integrated circuit having many functions as noted above. Consequently, many input and output units are required for communication with the exterior. In other words, the WSI wafer 1 needs to include a multiplicity of wire bonding pads 3 arranged peripherally thereof. As for the WSI package 2, a multiplicity of inner leads 6 and outer pins 8 must be arranged thereon.
On the other hand, there is a minimum to the area required for wire-bonding the wire bonding pads 3 and inner leads 6. That is, metal wires or the like are used for the bonding purposes. The bonds are formed by welding these wires to surfaces of the wire bonding pads 3 and inner leads 6. Thus, the wire bonding pads 3 or inner leads 6 must offer a minimum surface area for allowing the welds to be worked. Further, the circumferential length of the WSI wafer 1 is dependent on the size of the wafer. This inevitably sets a limitation to the number of wire bonding pads 3 that may be arranged peripherally of the WSI wafer 1. The number of inner leads 6 on the WSI package 2 also is limited for the same reason. This limitation to the number of pads is obstructive to formation of a WSI device including high-performance logic circuits or integrated logic circuits and memory circuits and requiring the number of pads beyond such limitation. As far as LSI is concerned, proposals have been made as to the chip construction for securing long circumferences of LSI chips. FIGS. 17 and 18 are perspective views of the LSI chips disclosed in Japanese Patent Laying-Open No. 63-198340. The example shown in FIG. 17 comprises an LSI chip 9 defining an opening 10 centrally thereof. A multiplicity of wire bonding pads 3 are formed on a surface peripherally of the LSI chip 9 and peripherally of the opening 10. In FIG. 18, a rectangular LSI chip 9 defines a cutout 11 on one side thereof. A plurality of wire bonding pads 3 are formed on a surface peripherally of the LSI chip 9 and peripherally of the cutout 11. In each of the illustrated examples, the region for arranging the wire bonding pads 3 is extended by utilizing the opening 10 or cutout 11. This allows an increase in the number of wire bonding pads 3.
Compared with LSI, WSI involves a large number of circuit tests in its manufacturing process. The circuit tests are carried out by placing testing probes in contact with the bonding pads 3 on the WSI wafer 1. At this time, the wire bonding pads 3 could be damaged by the tips of the probes. Wire bonding made on the surfaces of damaged wire bonding pads 3 in a subsequent process causes a wiring failure. This results in a low manufacturing yield. Since each WSI device is costly, a reduction in the manufacturing yield in particular is a serious problem. As one countermeasure it is conceivable to provide separately the wire bonding pads 3 and pads for circuit testing. However, as noted hereinbefore, there is a limitation to the number of pads formed on the conventional WSI devices, and hence it is difficult to provide pads for testing purposes.